Developed an accurate method of generating and simulating 3‑D NWFET structure in Sentaurus TCAD. It has been published at the IEEE‑EDTM conference. Also worked on developing an analytical model to predict VT distribution of NWFET due to LER

Publications

  1. An Accurate Structure Generation and Simulation of LER Affected NWFET

  2. Analytical model based estimation of line edge roughness induced VT variability in nanowire FETs